SPI0 control register.
| SPI_MEM_WDUMMY_DQS_ALWAYS_OUT | In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. |
| SPI_MEM_WDUMMY_ALWAYS_OUT | In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. |
| SPI_MEM_FDUMMY_RIN | In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. |
| SPI_MEM_FDUMMY_WOUT | In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. |
| SPI_MEM_FDOUT_OCT | Apply 8 signals during write-data phase 1:enable 0: disable |
| SPI_MEM_FDIN_OCT | Apply 8 signals during read-data phase 1:enable 0: disable |
| SPI_MEM_FADDR_OCT | Apply 8 signals during address phase 1:enable 0: disable |
| SPI_MEM_FCMD_QUAD | Apply 4 signals during command phase 1:enable 0: disable |
| SPI_MEM_FCMD_OCT | Apply 8 signals during command phase 1:enable 0: disable |
| SPI_MEM_FASTRD_MODE | This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. |
| SPI_MEM_FREAD_DUAL | In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. |
| SPI_MEM_Q_POL | The bit is used to set MISO line polarity, 1: high 0, low |
| SPI_MEM_D_POL | The bit is used to set MOSI line polarity, 1: high 0, low |
| SPI_MEM_FREAD_QUAD | In the read operations read-data phase apply 4 signals. 1: enable 0: disable. |
| SPI_MEM_WP | Write protect signal output when SPI is idle. 1: output high, 0: output low. |
| SPI_MEM_FREAD_DIO | In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. |
| SPI_MEM_FREAD_QIO | In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. |
| SPI_MEM_DQS_IE_ALWAYS_ON | When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. |
| SPI_MEM_DATA_IE_ALWAYS_ON | When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. |